The present invention relates to a semiconductor memory cell including multiple (more than two) transistors or multiple transistors physically merged into one unit, and to a process for fabricating the cell.
As a high density semiconductor memory cell, there has been made available a dynamic semiconductor memory cell known as a single-transistor semiconductor memory cell including one transistor and one capacitor like the one shown in FIG. 32. In such a semiconductor memory cell, the capacitance of the capacitor must be large enough so that electric charge stored in the capacitor is capable of generating a sufficiently large change in voltage on the bit line. As the planar dimensions of the semiconductor memory cell are reduced, however, the size of the capacitor created as parallel planar shapes must also be decreased. As a result, there is raised a problem that, when information stored in the semiconductor memory cell as electric charge stored in the capacitor thereof is read out, the read out information is buried in noise. There is also raised a serious problem that only a small change in voltage is generated on the bit line because the stray capacitance of the bit line increases each time a new generation of the semiconductor memory cell is introduced. As a means for solving the problems, there have been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure like the one shown in FIG. 33 or a stacked capacitor cell structure. However, there are fabricating-technological limits on the depth of the trench (or the groove) and the height of the stack, giving rise to factors limiting the capacitance of the capacitor of the semiconductor memory cell. For this reason, a dynamic semiconductor memory cell having such structures has reached the limit of a range of dimensions under the low sub-micron rule, without introducing high cost new materials for the capacitor.
As for the transistor employed in the semiconductor memory cell, in the planar dimensions under the low sub-micron rule, there are encountered problems such as deterioration of the voltage withstanding characteristic and a punch-through problem. It is thus much feared that a current leak is generated even if the voltage is still within a prescribed range. As a result, when a semiconductor memory cell is made infinitesimal in size, it is difficult to have a semiconductor memory cell having the related art transistor structure normally operate.
In order to solve the limit problems described above, the applicant of the patent application of the present invention has proposed a semiconductor memory cell including two transistors or two transistors physically merged into one unit as is disclosed in Japanese Patent Application No. Hei 5-246264 (Japanese Patent Laid-open No. Hei 7-99251). The semiconductor memory cell shown in FIGS. 15A and 15B of Japanese Patent Laid-open No. Hei 7-99251 includes a first semiconducting region SC.sub.1 of a first conductivity type in a surface region of a semiconducting substrate or on an insulating substrate, a first conductive region SC.sub.2 formed in a surface region of the first semiconducting region SC.sub.1 in contact with the first semiconducting region SC.sub.1 to form a rectifying junction in conjunction with the first semiconducting region SC.sub.1, a second semiconducting region SC.sub.3 of a second conductivity type formed in a surface region of the first semiconducting region SC.sub.1 separated away from the first conductive region SC.sub.2, a second conductive region SC.sub.4 formed in a surface region of the second semiconducting region SC.sub.3 in contact with the second semiconducting region SC.sub.3 to form a rectifying junction in conjunction with the second semiconducting region SC.sub.3 and a conductive gate G provided on a barrier layer. The conductive gate G serves as bridges between the first semiconducting region SC.sub.1 and the second conductive region SC.sub.4 as well as between the first conductive region SC.sub.2 and the second semiconducting region SC.sub.3. The conductive gate G is connected to a first wiring for selecting a semiconductor memory cell and the first conductive region SC.sub.2 is connected to a write-information setting line. The second conductive region SC.sub.4 is connected to a second wiring for selecting a semiconductor memory cell.
The first semiconducting region SC.sub.1 serving as a channel forming region CH.sub.2, the first conductive region SC.sub.2 serving as a source/drain region, the second semiconducting region SC.sub.3 serving as another source/drain region, and the conductive gate G compose a switching transistor TR.sub.2. On the other hand, the second semiconducting region SC.sub.3 serving as a channel forming region CH.sub.1, the first semiconducting region SC.sub.1 serving as a source/drain region, the second conductive region SC.sub.4 serving as another source/drain region, and the conductive gate G compose an information storing transistor TR.sub.1.
In an operation to write information in this semiconductor memory cell, the switching transistor TR.sub.2 is put in a turned-on state. As a result, the information is stored in the channel forming region CH.sub.1 of the information storing transistor TR.sub.1 as an electric potential or as electric charge. In an operation to read out information from the information storing transistor TR.sub.1, on the other hand, a threshold value of the information storing transistor TR.sub.1 seen from the conductive gate G varies dependently upon the electric potential or electric charge representing information stored on the channel forming region CH.sub.1 of the information storing transistor TR.sub.1. Thus, in an operation to read out information from the information storing transistor TR.sub.1, by applying an appropriately selected electric potential to the conductive gate G, the storage state of the information can be judged from the magnitude of a channel current (including a zero magnitude). The information is read out by detecting the operating state of the information storing transistor TR.sub.1.
To put it in detail, in an operation to read out information from the information storing transistor TR.sub.1, the information storing transistor TR.sub.1 is put in a turned-on or turned-off state, depending upon the information stored therein. Since the second conductive region SC.sub.4 is connected to the second wiring as described above, a current may or may not flow to the information storing transistor TR.sub.1, depending on whether the stored information is "0" or "1". In this way, information stored in the semiconductor memory cell can be read out by utilizing the information storing transistor TR.sub.1.
In an operation to read out information from the information storing transistor TR.sub.1, however, any control mechanism of the current flowing through the first semiconducting region SC.sub.1 sandwiched between the regions SC.sub.2 and SC.sub.3 is not introduced. Thus, when sensing the information storing transistor TR.sub.1 by using the conductive gate G, only a small margin of the current flowing through the first semiconducting region SC.sub.1 and the second conductive region SC.sub.4 is obtained, giving rise to a problem that the number of cells connected to a bit line is limited.